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TurboMMU040+_1.8.lha
Description: 
Developer:SpeedGeek
Homepage:http://eab.abime.net/showpost.php?p=1288238&postcount=1
Readme:
TurboMMU040+ 1.8 ©SpeedGeek 2020

INTRODUCTION:
TurboMMU040+ is an MMU tool to maximize the MMU performance of
most* 68040 and 68060 libraries. The MMU is a most excellent
and valuable feature of advanced 68K CPUs. Unfortunately, it's
usage does not come without any performance loss. How much
performance is lost depends on many factors, but this tool
deals specifically with the MMU configuration factors.

FEATURES:
- Enables 8K page mode MMU operation!
- Converts existing 4K page tables to 8K page tables
- Does NOT increase memory usage for MMU tables
- Enables (optional) ITTx management for 4GB of address
space!
- Uses 68040/060 library detection code
- 100% Assembler code

REQUIREMENTS:
- Amiga with 68040 or 68060 CPU and MMU
- 68040.library or 68060.library

DISCLAIMER:
Use at your own risk. No warranty expressed or implied, etc.

DISTRIBUTION:
This program is freely distributable but must include this
text file.

USAGE:
- Copy TurboMMU040 into your C: directory
- See WARNINGS to determine if FastCache040+ should be
installed first (Helpful messages are provided but no
warning code is returned if it is not installed).
- First disable or unmap any MMU remapped Kickstart ROM(s)!
- Execute it from the shell or...
- Add it to your startup-sequence (must be after Setpatch)
- The libraries default ITTx settings are maintained until
you use any of the following options:
1) To enable ITTx 4GB management use the ITTx option
2) To disable ITTx 4GB management use the NOITTx option
- If you want to get 4K page mode back you must reboot but
you can toggle the ITTx on/off as often as you like.
- Send the output to >NIL: to avoid seeing any text messages
- If the results are successful the return code = 0
- If the results are NOT successful the return code = 5

PERFORMANCE AND TECHNICAL ISSUES:
The 8K page size provides a 2x increase in the address space
which resides in the ATC. When a page address "Hits" in the
ATC it provides a "Zero" wait state address translation.
When a page address "Misses" in the ATC the MMU performs a
table search in memory to find the page address. Hence, many
wait states are incurred which result in a performance loss.
Both the 68040 and 68060 have a 64 entry ATC so 64 x 4K = 256K
and 64 x 8K = 512K.

The ITTx registers manage the instruction page descriptors
for a 16MB - 4GB size of address space. They are typically
disabled but may be enabled for part of the address space by a
few libraries. TurboMMU040 optionally enables it for the full
4GB of address space. This effectively bypasses the MMU
and provides "Zero" wait state performance for all instruction
translations. The ITTx usage trade off is the loss of the of
the performance benefit (if any) from remapping the Kickstart
ROM(s) into Fast memory. Also, if the library has already
enabled the ITTx you may want to keep the default settings.

WARNINGS:
************************************************************
Systems configured with a DMA driver MUST install
FastCache040+ before using this tool! Otherwise, the
CachePreDMA/PostDMA API of the 68040/060 library will assume
the 4K page size and fail to modify the correct pages
resulting in eventual data transfer errors!
************************************************************

Failure to disable or unmap MMU remapped Kickstart ROM(s)
will result in a loss of memory which can NOT be reclaimed
after conversion to 8K pages (YOU HAVE BEEN WARNED!).

Attempted usage of this tool with existing 4K MMU tools is
VERY risky! Some tools will check the page size and safely
exit, but others will just assume the page size is correct
and proceed to crash your system! Likewise, libraries which
have a built in API (e.g. Phase 5) should be used with
caution.

This tool does NOT always provide an identical memory map to
the original. Specific cases when mapping will change are:

1) MMU remapping of the Zero page area is 4K aligned (MMU
remapping is disabled).
2) SRP table differs from URP table (URP table replaces SRP
table).
3) The Kickstart MMU remap warnings have been ignored (All
physical ROM addresses are restored).

*Compatibility support for most 68040 and 68060 libraries does
NOT mean all of them!

NOTES:
The executable file name excludes the "+" character to avoid
problems with the Amiga Shell. See TurboMMUtools.txt for info
on the initial support tools.

UPDATE:
Added MapConTM060 1.0 to archive. MapConTM060 supports the
very proprietary TekMagic 68060.library. See MapConTM060.txt
for more info. Since v1.5 TurboMMU040+ allocates 16KB of RAM
to handle the (few) libraries which use 4K aligned remapping
of the $FFFF8000 space.

HISTORY:
v1.0 - First release
v1.1 - Added code to keep the Zero page remapping if it meets
the 8K alignment requirement (So you got a 50/50 chance)
v1.2 - Added code to compare Page table address at 8K blocks
vs. 4K blocks. This might improve indirect mapping
accuracy only since direct mapping is always converted
to the physical address.
v1.3 - Updated code to allow indirect mapping of the
"Extended" Zero page area. Added NOITTx option so the
libraries default ITTx settings can be maintained.
v1.4 - Added code to detect and report FastCache040+ as a
helpful reminder.
v1.5 - Added code to keep direct remapping of $FFFF8000 space
for libraries which don't use indirect. Lha_68K gets a
psuedo Enforcer hit for relying on MMU remapping here.
v1.6 - Added code to disable the DTTx registers. This is a
quick fix to support the very proprietary Apollo
68060.library. Apollo gets away with the default DTTx
enable only because the SCSI controller doesn't use DMA.
v1.7 - Fixed typo bug for ITTx options. Now shows 4GB size.
v1.8 - Added code to disable Zero page remapping when the Chip
RAM start addr is not remap compatible. Otherwise, OS3.1
systems in particular could crash if the Zero page was
remapped.
Screenshot(s):
Upload Date:Mar 29 2020
Category:System/Patchs/040-060
Download:TurboMMU040+_1.8.lha
Size:4 KB
Downloads:503
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