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FastCache040+ 2.4 ©SpeedGeek 2020

FastCache040+ is a patch to replace the CachePreDMA() and
CachePostDMA() functions of most 68040/060 libraries. While
the old functions are adequate they are far from optimal.
These old functions have 2x more code then the new ones
provided with this patch!

Also, the new functions implement a much more efficient method
of managing the Copyback cache for DMA. While every system
will have some CPU performance loss under DMA conditions, the
new functions keep this performance loss to a bare minimum.

- Replaces CachePreDMA() and CachePostDMA() with smaller
and more efficient code
- Replaces complex MMU code with simple and fast DTTR code
- Temporarily changes Copyback mode to Write Through for DMA
(but only when required!).
- Never flushes the ATC!
- Never flushes the DC for Chip RAM DMA!
- Uses 68040/060 library detection code
- Will not patch itself
- 100% Assembler code

- FastCache040+ 2.4 (NewFunc 190 bytes)
- 68060.library 46.7 (OldFunc 304 bytes)
- 68040.library 44.2 (OldFunc 414 bytes)

- Amiga with 68040 or 68060 CPU and MMU
- 68040.library or 68060.library

Use at your own risk. No warranty expressed or implied, etc.

This program is freely distributable but must include this
text file.

- Copy FastCache040 into your C: directory
- Execute it from the shell or...
- Add it to your startup-sequence (Must be AFTER Setpatch!)
- If the install is successful the return code = 0
- If the install is NOT successful the return code = 5

Do NOT use this patch with GigaMEM, VMM or any similar
virtual memory software! Do NOT use this patch with any
code which uses the MMU to write protect or remap modified
data structures!

Remapping a mirror image of the Kickstart ROM with the MMU
is OK! The new functions still have one thing in common with
the old functions. They do NOT translate virtual addresses
as specified in the Amiga RKRM! For more info on the old
functions see the Enforcer.guide by Michael Sinz.

FastCache040+ v1.7 has been removed. Phase5 68060.library
users can optionally use FixMapP5.

(Pre 2.0 history deleted)
v2.0 - Added code to enable only one DTTR when the Nest count is
one. Most systems have only one DMA driver and only need
to have 16MB of address space managed for this case.
Removed 1.9BR version which was over-rated due to most
DMA drivers operating at higher priority than typical
user tasks.
v2.1 - Reworked the code to fix a problem with Snoopy 2.0
(Aminet). Sorry, this version no longer supports 16 byte
aligned cache enabled MEMF_24BIT transfers. NOTE: The
original P5 library functions have problems with Snoopy
too. I suppose FastCache040+ 2.0 should remain available
for the non-snoopers.
v2.2 - The Snoopy fix broke MEMF_24BIT transfers. So another bug
fix was required. Let's hope it's the last.
v2.3 - The 16 byte alignment code is back and now avoids the
change of cache mode for this specific case. Removed
Continue case from PreDMA since the expected results are
the same as the Non-Continue case. The cache disable test
code was removed to save the overhead of this very
uncommon case.
v2.4 - Reworked PostDMA code to fix Nested call cache flush bugs.
We really don't want to forget about systems with multiple
DMA drivers do we?

Upload Date:Mar 09 2020
Size:2 KB